1. Field of the Invention
The present invention relates to a semiconductor memory including a plurality of memory cells, each of which is designated using a row address and a column address, and to a memory system including the same.
2. Description of the Related Art
A representative semiconductor memory in which a memory cell to be accessed among a plurality of memory cells is designated using a row address and a column address is a dynamic random access memory (DRAM). A DRAM has a feature that an access to a first column address which is designated first after a row address is designated (hereinafter, such an access will be referred to as a "row access") is performed at a relatively low speed and that an access to a column address subsequent to the first column address (hereinafter, such an access will be referred to as a "column access") is performed at a relatively high speed. Such a feature is based on the fact that an active state of a word line corresponding to a row address is time-consuming, but once the word line is activated, memory cells connected to the word line can be accessed at a relatively high speed.
For example, in the case where a DRAM is used as the main memory of a personal computer (PC), a memory controller performs one row access to the DRAM and then performs 3 or 7 column accesses (so-called page access). Thus, the access speed in a second cycle and later cycles is raised. A row access is performed in response to a desired row address and a desired column access. Column accesses are performed by sequentially changing column addresses while retaining the row address unchanged. Such row and column accesses are performed for line fill of an L1 or L2 cache.
After 4 or 8 cycles of accesses to the DRAM are completed, a memory controller changes the state of the word line corresponding to the row address from the active state into an inactive state. Then, the memory controller waits for the next access request to the main memory.
As methods for accessing a memory cell at a high speed, the following two are most commonly known.
According to a first method, data for all the column addresses corresponding to a plurality of row addresses are stored in an SRAM. This method is proposed by Enhanced Memory Systems Inc.
A DRAM adopting the first method can have, for example, four SRAM caches. Each of the four SRAM caches can store data for all the column addresses corresponding to a row address (hereinafter, referred to as "one-page data"). Accordingly, the DRAM can store 4-page data corresponding to four row addresses using the four SRAM caches.
In this manner, the first access of the 4 to 8 cycles which is generated for each cache line fill is performed at a higher speed as long as the access is performed to data for several pages stored in the SRAM caches.
According to a second method, a plurality of memory cells are divided into a plurality of banks, and the plurality of banks are independently accessed. This method is adopted in synchronous DRAMs and Rambus DRAMs which are being actively developed today.
A DRAM adopting the second method can have, for example, 8 or 16 banks. Each bank can hold one-page data by a sense amplifier. Accordingly, by maintaining the word line corresponding to the row address active, the access to the word line is made page access. As a result, the access speed to the first column address in a cache fill cycle is raised.
The above-described two methods both have a disadvantage in that the row access performed to read one-page data is too slow to significantly improve the memory performance.